1. Introduction
The rapid growth of large-scale AI infrastructure is placing unprecedented demands on modern datacenter networks.
As AI workloads become increasingly distributed, network devices are no longer responsible solely for forwarding packets but are expected to support communication, data processing and AI inference at line rate. This has driven growing interest in in-network computing, where computation is executed within network devices to reduce communication overheads, improve performance and increase resource efficiency.
Recent advances in programmable network devices have enabled in-network execution of AI tasks. JEWEL [1] demonstrates joint packet- and flow-level inference within programmable switches with tree-based AI models, while subsequent work such as FENIX [2] augments switches with FPGA accelerators to support more sophisticated deep neural network inference for more complex applications. This progression reflects a broader trend towards heterogeneous network devices that combine programmable switches with FPGA-based acceleration.
However, these systems remain statically configured, with hardware pipelines designed for specific applications. For example, programmable switches allow network operators to update forwarding rules, model parameters and table entries at runtime, but adapting to fundamentally different AI or network services often requires redesigning and redeploying the entire processing pipeline. FPGA-based network devices offer a compelling alternative [3]: rather than implementing a single fixed hardware pipeline, they can potentially support multiple hardware functionalities that are dynamically selected or reconfigured in response to changing network conditions and application demands.
Yet existing systems largely exploit FPGAs as static accelerators, treating reconfiguration as a hardware implementation mechanism rather than a network systems capability. Consequently, fundamental questions remain regarding how network devices should safely and efficiently adapt their hardware functionality to changing services, traffic patterns and operational requirements while maintaining line-rate performance and service continuity.
This project will investigate adaptive in-network computing using reconfigurable FPGA switches. The student will develop runtime mechanisms, programming abstractions and system architectures that enable FPGA-based network devices to adapt their hardware functionality while maintaining line-rate packet processing and service continuity.
2. Research Objectives
The project will address the following research objectives:
Develop adaptive in-network architectures that enable FPGA-based network devices to dynamically adapt their hardware functionality in response to evolving network conditions and application demands.
Design runtime systems and programming abstractions that support adaptive deployment, orchestration and reconfiguration of hardware functionality across heterogeneous network devices.
Demonstrate adaptive in-network communication and AI services on FPGA-based networking platforms, evaluating their performance, flexibility and sustainability compared to conventional static deployments.
3. Methodology
The research will combine network systems, FPGA design and experimental evaluation. The student will first develop an architectural framework for adaptive FPGA-based in-network computing, followed by runtime mechanisms that coordinate hardware adaptation while maintaining line-rate packet processing and service continuity. These ideas will be implemented on FPGA-based networking platforms and evaluated using representative AI communication and inference workloads to quantify improvements in adaptability, performance, resource utilisation and infrastructure longevity.
The project will equip the student with expertise spanning computer networks, in-network computing, FPGA architectures, hardware/software co-design, distributed systems and AI infrastructure.
4. Supervisory Expertise
The project, supervised by three members of the Cyberphysical Systems Research Group in the School of Electronics and Computer Science, brings together complementary expertise in network systems, reconfigurable computing and FPGA architectures.
Dr Aristide Akem has extensive expertise in programmable networks, in-network computing, SmartNICs and AI-driven network systems, providing leadership on network architectures and distributed AI infrastructure.
Dr Philippos Papaphilippou is an expert in FPGA architectures and FPGA-based network switches, with extensive experience in the design and implementation of high-performance reconfigurable networking hardware.
Professor David Thomas is an internationally recognised expert in reconfigurable computing, FPGA design methodologies and hardware/software co-design, bringing expertise in FPGA programming, hardware compilation and design automation for complex reconfigurable systems.
Together, the supervisory team provides a unique combination of expertise spanning network systems, FPGA architectures, reconfigurable computing and hardware/software co-design, ideally positioning the student to address the multidisciplinary challenges of adaptive in-network computing.
References:
[1] Akem, A. T.-J., Bütün, B., Gucciardo, M., and Fiore, M. Jewel: Resource-efficient Joint Packet and Flow Level Inference in Programmable Switches. In Proceedings of the IEEE INFOCOM 2024 – IEEE Conference on Computer Communications, 2024, pp. 1631–1640.
[2] Gao, X., Li, T., Zhang, Y., Wang, Z., Zeng, X., Yao, S., and Xu, K. FENIX: Enabling In-Network DNN Inference with FPGA-Enhanced Programmable Switches. In Proceedings of the 23rd USENIX Symposium on Networked Systems Design and Implementation (NSDI 2026), USENIX Association, 2026, pp. 867–882.
[3] Papaphilippou, P., Meng, J., Gebara, N., and Luk, W. Hipernetch: High-Performance FPGA Network Switch. ACM Transactions on Reconfigurable Technology and Systems, 15(1), 2021.