1. Introduction
Flexible electronics fabricated using, for example, Thin-Film Transistors (TFTs) are a promising technology for applications such as AI/ML at the edge. Such technologies often only implement N-type transistors, however, which is very inefficient in terms of energy.
This technology can, however, be used to design complex systems [1].
Adiabatic logic was proposed as a low power technology several decades ago. The underlying principle is that logic gates should only be turned on as they are needed and not turned off when they are active. This is achieved by using the clock, or multiple clock phases, as the power supply for logic gates. Adiabatic logic designs have been proposed that use both NMOS and PMOS transistors, but designs that use only NMOS transistors are possible. In order to achieve the promised energy efficiency, however, such circuits are very slow compared with modern CMOS technologies. This means that adiabatic logic has never achieved widespread acceptance. On the other hand, modern flexible electronics operate at relatively low frequencies. Thus, adiabatic logic may prove to be an appropriate technique for low power design in these technologies.
This project will look at how adiabatic logic can be used for AI/ML. We have already shown that the energy-efficient clock speeds of adiabatic logic are compatible with the clock speeds achievable in flexible electronics [2]. Nevertheless, formidable design challenges exist. Existing design tools are not compatible with adiabatic design styles. Signal paths need to be carefully balanced in order that the correct clock phases activate logic in sequence. In principle, some energy recovery is possible in adiabatic circuits, but we need to consider on-chip energy storage.
Therefore, this project will focus on how basic Processing Elements (PEs) can be joined with memory elements to build Convolutional Neural Networks (CNNs) in adiabatic logic. The PEs will be Multiply-Accumulate units (MACs) with limited memory that use reduced precision fixed-point arithmetic. If time permits, we would hope to fabricate and test a basic system.
References:
[1] Ozer, E., Kufel, J., Prakash, S. et al. Bendable non-silicon RISC-V microprocessor. Nature 634, 341–346 (2024). https://doi.org/10.1038/s41586-024-07976-y
[2] K. Chen, G. V. Merrett and M. Zwolinski, "Enabling Efficient Pure-NMOS Circuits Through Adiabatic Complementary Pass-Transistor Logic," 2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS), Paris, France, 2025, pp. 158-162, doi: 10.1109/NewCAS64648.2025.11107155.