Introduction
In various fields including healthcare, robotics, audio, and Internet of Things (IoT) devices, there is a significant surge in the need for high-throughput and ultra-low-power signal processing.
Traditional DSP engines find it challenging to keep up, whereas compact AI models are ready to provide enhanced accuracy with a reduced code footprint, provided we can effectively implement them on silicon for remote locations, edge devices, and sustainable applications.
Thus, we have the opportunity to re-envision how small silicon components can execute robust machine-learning algorithms using only hundreds of microwatts to milliwatts. Become a part of the Lab of Efficient Machine Intelligence to develop cutting-edge digital integrated circuits that provide sustainable and on-chip intelligence.
The project has the following three objectives:
(i) To architect and prototype network topologies tailored to large-scale deep learning driven signal processing algorithms. Novel topologies are supposed to provide load-aware distributed processing on the network, while enabling sustainable energy management.
(ii) To implement and validate the operation of the introduced networks in using FPGA. This step further helps translation of a FPGA design on silicon in a specific complementary metal-oxide-semiconductor (CMOS) technology (e.g. 180 nm).
(iii) To benchmark energy, performance and accuracy against the state-of-the-arts.
Our interest is to develop designs utilizing the steps (i) and (ii) for real-time and on-chip classification of biomedical signals, however, other applications can be identified. For example, we have already developed complex algorithms for brain-computer interfaces that can be translated into hardware using the proposed flow for low-power and sustainable uses.
About the candidate
This is an ideal project for a PhD student who enjoys problem solving and interdisciplinary research, involving network topologies, signal processing, machine learning, low-power hardware architectures and microelectronics design. The candidate will have the opportunity to learn many desirable knowledge and scientific skills during this PhD.
This is a 4-year integrated PhD (iPhD) programme and is part of the UKRI AI Centre for Doctoral Training in AI for Sustainability (SustAI). For more information about SustAI, please see: https://sustai.info/.
The candidate will have a chance to the training and networking opportunities offered through the CDT and to collaborate with a strong multidisciplinary team of academics at University of Southampton (UoS). There are also to state-of-the-art laboratory facilities from ECS (DHBE and SET) and Zepler institute. Applicant will be provided with access to MATLAB, FPGA board, Cadence software and fabrication facilities.